1. Field of the Invention
The present invention relates to a high-frequency switch which can be provided with high power handling capability, with a low loss, and at low costs.
2. Description of the Related Art
As an example of a high-frequency switch, FIG. 10 shows a circuit diagram of a high-frequency switch disclosed in “Monolithic AlGaN/GaN HEMT SPDT switch” IEEE 12th GaAs Symposium, pp. 83-86, 2004. The circuit is a double-pole single-throw switch in which field effect transistors (hereinafter, referred to as “FET”) connected in series with an output terminal COM are connected to two sets of an FET connected in parallel and an input terminal. In the circuit, by applying a voltage to control signal terminals V1 and V2, FETs Q1 to Q4 are caused to have a transmission property or an isolation property, whereby a path of a high-frequency signal is switched. Further, the circuit has characteristics in which power handling capability of the switch can be increased by an increase of each gate width of the FET Q1 and FET Q2 that are connected in series with each other and by an increase of each saturation current.
However, when the switch having high power handling capability is configured with the above-mentioned configuration, there arises a problem in that a transmission loss at an input of low power is increased as each gate width of the FETs connected in series with each other is increased in order to increase the power handling capability. For example, in FIG. 10, in a case where the high power handling capability is required so as to obtain a transmission state between an IN1 and the COM, it is necessary to increase the gate width of the FET Q1. However, the FET having a large gate width generally has a low isolation property. Accordingly, when the gate width of the FET Q1 is increased, a state between the IN1 and the COM is set to an isolation state, and a high-frequency signal from an IN2 leaks into the IN1 side when a state between the IN2 and the COM is set to the transmission state. As a result, the transmission loss between the IN2 and the COM is increased. The circuit has a symmetric configuration, so a similar problem also arises when the high power handling capability is required between the IN2 and the COM.